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[Other] m序列

Description: Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
Platform: | Size: 5120 | Author: 张林 | Hits:

[VHDL-FPGA-Verilog] zzmodelsim

Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
Platform: | Size: 505856 | Author: oasis | Hits:

[VHDL-FPGA-Verilog] bpsk

Description: 基于bpsk的vhdl语言编程与性能仿真-Based on the vhdl language bpsk programming and performance simulation
Platform: | Size: 205824 | Author: matt | Hits:

[Communication-Mobile] bpsk

Description: These code are some matlab codes for BPSK modulator and demodulator in fading channels for wireless communications
Platform: | Size: 363520 | Author: Abbas | Hits:

[VHDL-FPGA-Verilog] 50846288C

Description: verilog 硬件编程实现bpsk调制-verilog hardware, programming bpsk Modulation
Platform: | Size: 51200 | Author: 凡要林 | Hits:

[Communication] examples

Description: 二进制差分编码解码，二进制差分相移键控二进制幅移键控，二进制相移键控，二进制频移键控最小频移键控的调制与解调-Differential encoding and decoding binary, binary differential phase shift keying binary amplitude shift keying, BPSK, binary frequency shift keying Minimum Shift Keying modulation and demodulation
Platform: | Size: 5120 | Author: xvlu | Hits:

[Other] bpsk

Description: 基于能量检测的频谱感知.由于实际信道中的多径和阴影效应，单个认知用户频谱感知的性能受到影响，因此需要靠不同用户间的协同频谱感知来对抗多径和阴影效应。本设计要求在文中采用一种协作机制，即两用户进行协作频谱感知，提高主用户的检测率，减少检测时间，并且得到捷变增益。要求给出仿真结果。-spectrum sensing in cognitive radio based on energy detection.As the channels in diameter and shadow, not a single user spectrum of capabilities and therefore need different between a user to the spectrum is perceived as more and the effect. this design for the use of a coordination mechanism, the two users collaborate spectrum, the detection rate of increase and decrease the test of time and get a change requires immediate gain. some emulation.
Platform: | Size: 281600 | Author: 林熙怡 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。-Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.
Platform: | Size: 40960 | Author: 徐向斌 | Hits:

[matlab] BCH[31-16]-with-BPSK-MFSK

Description: comperation of performance of BCH [31 16] code with BPSK and MFSK
Platform: | Size: 12288 | Author: kantaria | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.BPSK3中程序的目的是：将m序列通过滚降系数为0.3的升余弦滤波系统后的信号采样输出。 3.BPSK5中程序的目的是：将m序列通过滚降系数为0.5的升余弦滤波系统后的信号采样输出。 4.以上两个程序的运行平台为Quartus（verilog语言）。-BPSK modulation is used to design, as follows: 1.matlab.txt the program is under matlab platform. Mat format. Purpose is to output a 64* 4 matrix, each element is an integer between 0 and 255. Matrix of each line is a symbol of four the number of sampling points of the four quantitative value. However, due to the current symbol by raised cosine filtering system, before and after a total of six yards by the combined effect of element, it is shared by the six yards per decision. The 6 symbol is random, may be 0 may be 1 (may be bipolar may be+1-1), so a total of six yards per 2 ^ 6 = 64 kinds of situations, so the resulting matrix 64* 4. Finally, the number of progressive output of the 256. 2.BPSK3 purposes of the procedure is: m sequence of roll-off factor of 0.3 by the raised cosine filter system output after the signal sampling. 3.BPSK5 purposes of the procedure is: m sequence of roll-off factor of 0.5 by the raised cosine filter system output after the signal sampling.
Platform: | Size: 4096 | Author: | Hits:

[Other] BPSK

Description: Use the verilog language to module the psk.
Platform: | Size: 4068352 | Author: YU MING SUN | Hits:

[VHDL-FPGA-Verilog] ad9850

Description: 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波，13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
Platform: | Size: 1415168 | Author: chen | Hits:

[3G develop] BPSK_receiver

Description: BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
Platform: | Size: 20480 | Author: bigdot | Hits:

[VHDL-FPGA-Verilog] DDS_BPSK

Description: 基于DDS的BPSK调制器设计Verilog源码- U57FA u4E8.08 u868
Platform: | Size: 45833216 | Author: 不言中 | Hits:

[Other] BPSK_ASIC.tar

Description: BPSK demodulator ASIC design with Toshiba 45nm lib in verilog for EE 287 Spring 2013
Platform: | Size: 1823744 | Author: mgyuli | Hits:

[Other] bpsk

Description: BPSK modulation technique for 1 sign bit and other the original output form. if input bit is 1; output is 01 if input bit is 0; output is 11
Platform: | Size: 140288 | Author: twinki | Hits:

[VHDL-FPGA-Verilog] demodulation

Description: 基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
Platform: | Size: 131072 | Author: 涛2017777 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 先用Matlab理论仿真，得出滤波器系数。再用Verilog语言在ISE环境下编写程序，通过Modelsim和ChipScope进行波形仿真和引号抓取，从而提高调试的效率。通过手机发送指令来控制上下变频器的参数。(Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under ISE environment. Waveform simulation and quotation mark grabbing are carried out through Modelsim and ChipScope, so as to improve the efficiency of debugging. The parameters of up-down converter are controlled by sending instructions from mobile phone.)
Platform: | Size: 6740992 | Author: 财哥在此 | Hits:

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